Design and Performance Evaluation of SRAM Processing in Memory Using TSMC 90nm CMOS Technology
VERSION OF RECORD ONLINE: 18/09/2025
Corressponding author's email:
khoapv@hcmute.edu.vnDOI:
https://doi.org/10.54644/jte.2025.1797Keywords:
Static random access memory, 8T-SRAM cell design, SRAM processing on memory, 8T-SRAM processing on memory, Power consumptionAbstract
Memory is a crucial component in electronic circuits, especially in embedded devices. With the rapid development of AI and Machine Learning, the demand for processing large amounts of data has exposed the limitations of CPUs and the high costs of GPUs. The Processing-In-Memory (PIM) architecture addresses the bottleneck issue by integrating processing capabilities directly into memory. Static random-access memory (SRAM), a high-speed memory type, is commonly used as cache and main memory in CPUs. Integrating processing directly into SRAM, SRAM-based processing in memory enhances performance and alleviates bottleneck problems. In this study, the design and evaluation of two 64-bit SRAM Processing-In-Memory architectures were implemented on TSMC’s 90nm technology using Cadence Virtuoso software. Computational operations, such as ternary multiplication, were simulated and analyzed its power consumption under PVT conditions evaluate the stability and accuracy. The research results provide a deeper understanding of SRAM-based in-memory processing design, improve knowledge and skills in circuit design, and propose further developments for SRAM Processing-In-Memory in the future.
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