Design and Verification of an SPI-Wishbone Controller
Corressponding author's email:
tandd@hcmute.edu.vnDOI:
https://doi.org/10.54644/jte.71B.2022.1142Keywords:
SPI standard, Wishbone bus, FPGA, Verilog, TestbenchAbstract
SPI (Serial Peripheral Interface) is a synchronous serial communication standard for connecting and transferring data between electronic devices proposed and developed by Motorola Inc. The main advantages of SPI standard are high data transmission speed, synchronization, simple connection, and low logic resources. Furthermore, Wishbone is a popular bus standard with open source codes, widely used in Silicore Corporation's projects. In this paper, we present a detailed design of a controller called SPI-Wishbone, which communicates with peripheral devices based on the SPI standard that can be configured in either Master mode or Slave mode. The designed module can be controlled, transmit, and receive data from a central processing unit via Wishbone bus. Finally, we conduct extensive simulation results and a summary of logic resource usage and power consumption to validate the functionality and effectiveness of the proposed design. We use Verilog Hardware Description Language in the design and simulation processes of the SPI-Wishbone module.
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