Dedicated SoC Peripheral Design for Power Control Applications on the Xilinx Ultrascale+ Platform

Published online: 09/10/2025

Abstract

This paper presents the design, implementation, and validation of a high-performance, configurable control architecture exploiting the heterogeneous computing fabric of the Xilinx UltraScale+ MPSoC XCZU3CG. Targeting demanding real-time applications like multi-level power converters, the core contribution is an optimized hardware/software partitioning strategy. We detail the tight integration of the ARM Cortex-A53 Processing System (PS) with custom parallel processing elements synthesized within the Programmable Logic (PL). The implemented VHDL-based PL architecture features multiple independent controller modules, achieving significant parallelism and providing 176 precisely controlled ePWM outputs crucial for fine-grained actuation. A key design element is the robust PS-PL AXI interface, facilitating efficient run-time parameter configuration of hardware controllers from the PS, enhancing operational flexibility. The design methodology prioritized deterministic low-latency performance alongside optimized PL resource utilization. The register interface intentionally mirrors familiar DSP conventions to ease system integration. Experimental results successfully validate the MPSoC architecture's functional correctness and performance metrics, demonstrating its effectiveness for substantially accelerating the design cycle for complex embedded control systems, The system-on-chip (SoC) was validated using a pulse generation configuration across ten sets of T-Type three-level inverter configurations, resulting in a total of 120 pulse-width modulation (PWM) outputs.