Common-Mode Voltage Reduction Control Method With Offset Voltage Function for Five-Level Inverter

Abstract

High Common Mode Voltage (CMV) is recognized as the primary cause of a range of operational issues including leakage current, accelerated bearing wear, electromagnetic interference, and an overall decline in both the performance and reliability of drive devices. Numerous studies have concentrated on mitigating the effects of CMV through various modulation techniques, such as space vector modulation, which have been widely researched. However, these techniques typically require a significant amount of computational effort and impose high control complexities on the system. In this study, an innovative approach is proposed to reduce CMV in a five-level Neutral Point Clamped (NPC) inverter by utilizing a discontinuous carrier Pulse Width Modulation (DPWM) technique enhanced with an offset voltage function. This DPWM method simplifies the computational process by incorporating an offset voltage function—calculated based on specific conditions for CMV reduction—directly into the modulation signal. The switching states of the semiconductor devices are then determined through a comparative analysis between the modulation signal and a high-frequency carrier waveform. The effectiveness of this method is conclusively demonstrated through simulation results, thereby highlighting its potential to improve both the operational efficiency and reliability of drive systems.