Design, Simulate, and Layout for a Static Random-Access Memory (SRAM) Using a 6T Memory Cell and a Latch-Based Sense Amplifier
VERSION OF RECORD ONLINE: 12/09/2025
Corressponding author's email:
khoapv@hcmute.edu.vnDOI:
https://doi.org/10.54644/jte.2025.1533Keywords:
6T SRAM, Power consumption, Sense Amplifier, Signal Noise Margin, DelayAbstract
This research study focuses on the implementation and assessment of a 64-bit SRAM (Static Random-Access Memory) design utilizing 6T memory cells. The objective of this SRAM design, as presented in this study, is to explore its structure, functionality, and key attributes. To achieve this, the Cadence Virtuoso tool is employed for both design implementation and evaluation, utilizing the CMOS technology library. The design incorporates 6T memory arrays, which are commonly used in modern SRAM designs, along with additional peripheral components for efficient array management. The memory circuit will be constructed using the Virtuoso Schematic Editor, and its physical layout will be created using the Virtuoso Layout Suite XL. The read and write operations are validated through timing diagrams for various scenarios. Furthermore, the stability of the 6T memory cells is ensured by conducting an SNM (Static Noise Margin) analysis. From a layout perspective, each component undergoes thorough verification for Design Rule Checking (DRC) and Layout vs. Schematic (LVS) using the Assura tool.
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References
W. M. Arden, "The international technology roadmap for semiconductors—perspectives and challenges for the next 15 years," Current Opinion in Solid State and Materials Science, vol. 6, no. 5, pp. 371-377, 2002.
V. T. Tri, "A design of 32kb SRAM combining row and column redundancy," The University of Danang - Journal of Science and Technology, vol. 5, no. 05, pp. 161-165, 2015.
T. N. P. Phu, D. P. G. Han, N. C. Luong, and N. V. Cuong, "Design a synchronous single-port SRAM 1024x32xmux4 using 28nm technology," International Journal of Computing and Digital Systems, vol. 10, no. 1, pp. 103-109, 2021.
M. Agarwal and T. Tevatia, “Design & Implementation Of Self Time Dummy Replica Technique In 128x128 Low Voltage SRAM,” Int. J. of Novel Research And Development, vol. 2, no. 4, 2017.
G. M. S. Reddy and P. C. Reddy, "Design and implementation of 8k-bits low power SRAM in 180nm technology," Proc. IMCECS, vol. 2, pp. 1-8, 2009.
G. Jain, “Design and Simulation Low Power SRAM Circuits,” International Journal for Scientific Research & Development, vol. 1, 2013.
W. Lim, H. C. Chin, C. S. Lim, and M. L. P. Tan, "Performance evaluation of 14 nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis," Journal of Nanomaterials, pp. 105-105, 2014.
P. V. Khoa and N. D. Thong, "Performance analysis of SRAM designs using TSMC 90nm CMOS technology," The University of Danang - Journal of Science and Technology, vol. 20, pp. 26-31, 2021.
N. Verma, "Analysis towards minimization of total SRAM energy over active and idle operating modes," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 9, pp. 1695-1703, 2010.
H. C. Chow and S. H. Chang, "High performance sense amplifier circuit for low power SRAM applications," In 2004 IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. II-741, 2004.
B. Rawat and P. Mittal, "A latch-based sense amplifier with improved performance for single ended SRAM application," Physica Scripta, vol. 98, no. 6, 2023.
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