Carrier PWM algorithm for five-level H-brigde npc inverter with switching reduction - Quach Thanh Hải; Tran, Thu Hà; Danh, Tuấn Lê; Do, Đức Trí; Le , Huỳnh Lý (Journal of Technical Education Science, 2015)
This paper presents the carrier pulse width modulation with a novel offset based to re- duce the number of switching times in a five-level H-bridge neutral point clamped inverter. The proposed technique uses the offset which is 3rd voltage component to shift the control voltage signal to the maximum or minimum amplitude of the carrier in order to reduce the intersection of the control signals and the carrier wave and thus to reduce the number of switching times. With the pulse width modulation method and flexible offset voltages in this study, the number of switching times/phase in a cycle can be reduced to 33%. Simulation and experimental results are provided in order to validate the proposed method.